One embodiment of the present invention relates to static memories or multi-port register files. More specifically, one embodiment of the present invention relates to very small swing high performance asynchronous CMOS static memory having a column multiplexing scheme.
Currently, memories or register files are widely used in numerous applications in various industries. Although, typically it is desirable to incorporate as many memory cells as possible into a given area, some known memories or register files are often perceived as physically too large (i.e., they take up too much silicon area) and/or are too slow for a given product definition. In addition, power dissipation is another parameter that all memory designers are forced to consider in order to make a product cost effective. Additionally, some applications demand that such memories or register files function synchronously or asynchronously.
One type of basic storage memory or register file is the CMOS static random access memory (alternatively referred to as the “SRAM”), which retains its memory state without refreshing as long as power is supplied to the cell. In one embodiment of a SRAM, the memory state is usually stored as a voltage differential within a bistable functional element such as an inverter loop. However, some currently known SRAM memories don't work in conjunction with low supply voltages. That is, as the supply voltage approaches about 1.0 volt or less, the access time increases exponentially. Moreover, such currently known SRAM memories are susceptible to noise. That is noise may be present, on a bitline for example, and may false trip one or more associated devices such as sense amplifiers.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.